Many modern integrated circuits are designed to perform their operations in response to input signals which are applied to terminals at relatively high frequencies (e.g., on the order of tens of MHz), and in an asynchronous or unclocked manner. One type of such integrated circuits is a static random-access memory, commonly referred to as an SRAM. SRAMs are designed to receive address values at address terminals, and to statically provide read or write access to the memory cells corresponding to the value of the address applied thereto. Accordingly, such SRAM circuits are designed to quickly respond to the address value applied thereto, without relying on a clock signal indicating that the value at its address terminals is valid.
In addition, it should be noted that the timing of address signals presented to an SRAM can vary widely. For example, a series of addresses may be presented to the SRAM at a high rate (e.g., 20 MHz), followed by a relatively long period of inactivity at the address terminals. During the period of inactivity, conventional fully static SRAMs maintain access to the memory cells selected by the address value which is maintained at the address terminals (unless otherwise controlled by a chip select or output enable signal).
In order to reduce power during such relatively long periods at which the address values are not changing, and also to provide the performance benefits of internal dynamic operation, many modern SRAMs include an address transition detection (ATD) circuit. The ATD circuit detects transitions at certain inputs to the SRAM, particularly the address terminals, and generates an internal signal responsive to detecting such a transition. The use of an ATD circuit allows the SRAM circuit to perform certain internal operations, such as precharging bit lines, deselecting sense amplifiers, and the like, after detection of the address transition, but before the decoders access the desired cell; alternatively, these internal operations may be done after a timeout period has expired in a memory cycle. Upon presentation of a new memory address to the SRAM, the transitions at the address terminal cause the ATD circuit to enable the necessary functions of the SRAM to access the memory cells selected by the new memory address. Examples of SRAMs controlled by such an ATD circuit are described in Okuyama et al., "A 7.5-ns 32K.times.8 CMOS SRAM," IEEE J. Solid State Circuits, Vol. 23, No. 5 (October 1988), pp. 1054-1059, Kohno et al., "A 14-ns 1-Mbit CMOS SRAM with Variable Bit Organization," IEEE J. Solid State Circuits, Vol. 23, No. 5 (October 1988), pp. 1060-1066, and Williams et al., "An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation", IEEE J. Solid State Circuits, Vol. 23, No. 5 (October 1988), pp. 1085-1094, all incorporated herein by this reference.
For such circuits as SRAMs, including those which utilize an ATD circuit, noise or other spurious signals at the input terminals can cause significant problems, if the circuit attempts to respond to the spurious signal. This is due to the design of these circuits to respond to unclocked signals, such as addresses; in contrast, clocked circuits receive a clock signal indicating, for example, that the value at the address terminals is valid, allowing the circuit to ignore noise and other transitions at these terminals at other times in the cycle.
In particular, if high frequency address transitions are applied to some conventional SRAMs, whether intentionally applied or resulting from noise, "race" conditions in these memories can improperly energize multiple word lines in the memory array, causing destruction of the stored data in some memory cells, as well as potential high current damage in the circuit. Prior techniques, including the forcing off of all wordlines during the latter part of the memory cycle (e.g,. during equilibration), may not be effective to defeat multiple word line selection if the response of the address input buffers is sufficiently fast.
Additional problems in SRAM devices may also be caused by high frequency address transitions. During a write operation, the address value must be maintained for a period of time after application of the write enable signal to allow time for the input data to reach the selected memory cell. In the event of noise at the address terminals of sufficient amplitude to cause a transition during such a write operation, data may be written into the wrong memory location. Also, high frequency address terminal transitions during a read operation may cause undesired transitions at the output terminals of the SRAM circuit. These transitions generate additional noise which may cause further undesired transitions in the circuit, and potentially resulting in oscillation of the circuit.
It is therefore an object of this invention to provide control of the input buffers of an integrated circuit so that high frequency transitions are ignored.
It is a further object of this invention to provide control of the input buffers of an integrated circuit in such a manner that timing constraints and race conditions resulting from address transitions, for example at the end of a write operation, are alleviated.
It is a further object of this invention to provide such control in a manner which does not significantly slow down the operation of the circuit to valid input transitions.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to this specification, together with its drawings.